Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory, among others.
Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Uses for flash memory include memory for personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices. This information can be used in personal computer systems, among others.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged
A NAND array architecture arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are coupled by rows to word select lines. However each memory cell is not directly coupled to a column bit line by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a source line and a column bit line.
Memory cells in a NAND array architecture can be configured, e.g., programmed, to a desired state. That is, electric charge can be placed on or removed from the floating gate of a memory cell to put the cell into a number of stored states. For example, a single level cell (SLC) can represent two binary states, e.g., 1 or 0. Flash memory cells can also store more than two binary states, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110. Such cells may be referred to as multi state memory cells, multibit cells, or multilevel cells (MLCs). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one bit. MLCs can have more than one programmed state, e.g., a cell capable of representing four bits can have fifteen programmed states and an erased state.
The state of a memory cell, e.g., the data stored in the cell, is determined by the threshold voltage (Vt). As an example, in a SLC, a Vt of 0.5V can indicate a programmed cell while a Vt of −0.5V might indicate an erased cell. A MLC includes multiple Vt windows that can each indicate a different state.
In MLCs, it is important that the Vt distributions be sufficiently spaced apart so as to reduce the possibility of a higher voltage of one distribution overlapping a lower Vt of the next distribution. The overlap can occur due to factors such as noise, floating gate coupling, or temperature variations of the integrated circuit, among various other factors. One way to create larger gaps between the various Vt distributions is to make the distributions themselves narrower. This can be difficult because memory cells program at different rates, e.g., Vts increase at varying rates, due to factors such as manufacturing process variations and/or repeated programming and erasing, among other factors.
A fast cell can have a higher threshold voltage than a slow cell, for a given programming period. Therefore, faster memory cells may be programmed before the slower cells since the faster cells can require fewer programming pulses. This can result in the Vt distribution for the faster cells being different than the Vt distribution for slower cells and/or closer to other Vt distributions due to the wider Vt distributions that can be created by faster cells.
One method to improve the above problems caused varying Vt rates of fast and stow memory cells is illustrated in U.S. Pat. No. 6,643,188 to Tanaka et al. and assigned to Toshiba and SanDisk Corporation. Tanaka et al. disclose a two-step programming method that uses first and second step verify voltages. Once a Vt for a memory cell being programmed reaches the first step verify voltage, a write control voltage is changed for all cells being programmed. This method can slow down the programming of all the memory cells, which can reduce programming throughput. That is, reducing the programming speed of all of the cells being programmed increases the time it takes to program all of the cells, whether the cells are fast cells or slow cells.
Another method that may be used to create narrower Vt distributions is to adjust the programming pulse step voltage as the cell Vt approaches a programmed state. However, this also can reduce programming throughput by requiring more programming pulses, e.g., due to a smaller incremented pulse step, which can slow the programming for all of the cells.
For the reasons stated above, and for other reasons stated below, which will become apparent to those skilled in the art upon reading and understanding the present disclosure, it can be beneficial to generate narrow memory cell Vt distributions while maintaining adequate programming throughput of a memory device.